1. Field of the Invention
The present invention relates to semiconductor devices having transistors formed on a semiconductor substrate such as a silicon-on-insulator (SOI) substrate and also to fabrication methods thereof.
2. Description of the Related Art
Semiconductor devices are such devices as metal oxide semiconductor (MOS) transistors formed on a semiconductor substrate. Examples of the semiconductor devices are logic circuits and memories such as dynamic random access memory (DRAM). Recently, there is proposed a semiconductor device performing dynamic memory by use of a simpler cell structure for the purpose of replacement of conventional DRAMs (see JP-A-2002-246571 (FIG. 25)). A memory cell is constituted from a single transistor having a floating body (channel body). This memory cell performs two-value storage while letting a state in which majority carriers are accumulated at the body be as a first data state (for example, logic “1” data) and letting a state in which the majority carriers are drawn out of the body be a second data state (e.g., data “0”).
This type of memory cell is known as the “floating body cell (FBC)”; a semiconductor device using FBCs is called the “FBC memory.” The FBC memory does not necessitate the use of any capacitors unlike ordinary DRAMs so that it offers advantages which follow: a memory cell structure is simple; a unit cell area stays less; and, for this reason, higher integration is made easier.
An SOI substrate is known as the substrate of a semiconductor device. FBCs are formed on an SOI substrate. The SOI substrate is structured so that a silicon layer with a single-crystal structure is disposed on or above a buried oxide layer that is formed on a “base” substrate. The substrate and the silicon layer are dielectrically separated or isolated from each other by the buried oxide layer. The use of such SOI substrate results in accomplishment of advantages such as speed-up of operating speeds, power saving abilities and others.
However, even in the case of using the SOI substrate, when MOS transistors are scaled down and miniaturized in size, a leakage current increases due to the presence of the so-called “short channel” effects. As a technique for avoiding this problem, a scheme is known for employing MOS transistors of the double gate type, which are structured so that the channel body of a transistor is sandwiched by two, upper and lower gate electrodes (see JP-A-14-57337 (FIG. 5)).